MENÜ MENÜ
  • Sie verwenden einen veralteten Webbrowser, weshalb es zu Problemen mit der Darstellung kommen kann. Bei Problemen mit der Bestellabgabe können Sie gerne auch telefonisch bestellen unter: 01805 / 30 99 99 (0,14 €/Min., Mobil max. 0,42 €/Min.)

Design of Reconfigurable Decoder for SRAM

Noor:Design of Reconfigurable Decoder f
Autor: Arti Noor / Sampath Kumar V. / Abhinav Vishnoi
Verfügbarkeit: nur noch 3 lieferbar
Artikelnummer: 865413
ISBN / EAN: 9783659114168

Verfügbarkeit: sofort lieferbar

49,00
Inkl. MwSt. , zzgl. Versandkosten

Zusatzinformation

Produktbeschreibung

Decoder design consists of choosing the optimal performance circuit style, providing flexibility in configuration of different sizes, sizing of transistors, adding buffers and consideration of fan outs. In this work, high speed reconfigurable decoders of different styles are analyzed for different loads of memory blocks. The power dissipation, delay, frequency & Vdd of various logic styles are analyzed. Evaluation of delay is done by changing Vdd, Speed is improved and power dissipation is minimized by a sizing technique. The memory system plays crucial role in determining optimum performance, power, speed and cost of the simple to complex machines. To improve the access time in memory system, there is requirement of configurable logic block which can be used to select rows and columns of partitioned memory blocks. In a memory for accessing and locating any random data, address decoders are used. The decoder block is contributing in access time and power consumption of memories. In this work, a reconfigurable decoder is proposed to select fewer word lines and to avoid large word line / bit line capacitance.

0 Kundenmeinungen

Bitte schreiben Sie uns Ihre Meinung zu: Design of Reconfigurable Decoder for SRAM

  • Wenn Sie dieses Eingabefeld sehen sollten, lassen Sie es leer!

Sie könnten auch an folgenden Produkten interessiert sein